Integrated circuit fabrication technology continually improves, and consequently, transistors continue to shrink in size. As such, more transistors and more complicated circuits can be fabricated on an integrated circuit die, or alternatively, on a smaller die to be used in a given circuit. Smaller transistor size also supports faster operating speeds and provides other benefits. For on-die memories (e.g., dynamic random access memory (DRAM)), a major issue with shrinking transistor size is standby power, as smaller transistor geometry results in higher electric fields, which stresses a transistor and causes oxide breakdown. Furthermore, on-die memory circuits are typically subject to leakage that could cause stored information to be discharged unless the memory circuits are periodically refreshed, which can increase the power that on-die memory circuits consume. Accordingly, a lower power supply voltage is often used for smaller geometry transistors to decrease the electric field. However, the lower power supply voltage also increases the delay of the transistors, which undesirable for high-speed circuits. To reduce the delay and improve operating speed, one approach is to reduce the threshold voltage (Vt) at which the transistors turn on. However, the lower threshold voltage and smaller transistor geometry result in higher leakage current, which is the current passing through a transistor when it is turned off. As such, because on-die memories typically occupy a large portion of area and contribute towards overall chip-leakage power, memory leakage power is often a significant fraction of wasted power, which can be especially problematic for wearable devices, health monitors, low-power sensors, cellular phones, and other devices where battery life is extremely important.
Furthermore, many modern mobile devices have substantial bandwidth and performance demands, which can exacerbate problems that relate to high power consumption. In particular, although the power that memory circuits consume can differ depending on the power mode or state associated with the memory circuits, the power mode or state can increase memory access latency and otherwise impact overall system performance. For example, a “power-down” state may use the least power and result in minimal to no leakage power. However, the “power-down” state shuts the memory circuits off such that the memory circuits cannot be accessed. On the other hand, in an “operational” state, the memory circuits consume more power and consequently contribute more towards overall leakage power, although in the “operational” state the memory circuits are accessible and ready to respond to memory access requests. Furthermore, transitioning between different power states or otherwise moving memory blocks between different power states tends to require power and time, which can increase memory access latency and compromise performance, especially in the event that memory power state transitions are frequent.